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AUSTIN SEMICONDUCTOR, INC. ADVANCE INFORMATION Austin Semiconductor, Inc. 512K x 32 Module nvSRAM
5.0V High Speed SRAM with Non-Volatile Storage
FEATURES * -55oC to 125oC Operation * True non-volatile SRAM (no batteries) * 20 ns, 25 ns, and 45 ns access times * Automatic STORE on power down with only a small * * * * * * *
capacitor STORE to QuantumTrap(R) nonvolatile elements initiated by software, device pin, or AutoStore(R) on power down RECALL to SRAM initiated by software or power up Infinite Read, Write, and Recall cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 5.0V 10% power supply Ceramic Hermetic 68 Quad Flatpak -Can order with X7R CAPS on package -Matches compatible pinout footprint of SRAM & EEPROM Module
AS8nvC512K32
nvSRAM
AVAILABLE AS MILITARY SPECIFICATIONS
* Military Processing (MIL-STD-883C para 1.2.2) * Temperature Range -55C to 125C
FUNCTIONAL DESCRIPTION
The Austin Semiconductor AS8nvC512K32 is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits for each of 4 die to form 512Kx32. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
LOGIC BLOCK DIAGRAM m[1, 2, 3] 4x 4x
DQ0-DQ31
(1-4)
28 29 30 31
(1-4)
AS8nvC512K32 Rev. 0.0 08/09
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PIN ASSIGNMENT (Top View)
CS
AS8nvC512K32
M4 M3 M2
VCAP 1
nvSRAM
MILITARY PINOUT/BLOCK DIAGRAM
68 Lead CQFP (Q)
VCAP A0 A1 A2 A3 A4 A5 CS3\ GND CS4\ WE1\ A6 A7 A8 A9 A10 Vcc
CS
HSB 2
Vcc A11 A12 A13 A14 A15 A16 CS1\ OE\ CS2\ A17 WE2\ WE3\ WE4\ A18 NC HSB\
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31
CS
CS
M1
Notes: 1. This pin left open if ordered with capacitors already mounted in package. 2. HSB\ signal is wired to all 4 die in module. This can be left open if not used.
Pin Name A0 - A18 A0 - A17 DQ0 - DQ7 DQ0 - DQ15 DQ16 DQ23 DQ24 DQ31 WE\1 4 CE\1 4 OE\ VSS VCC
I/O Type Input
Description Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data I/O Lines for die M1 (DQ0 7), M2 (DQ8 15), M3 (DQ16 23), M4 (DQ 24 31) Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tri stated on deasserting OE HIGH. Ground for the Device. Must be connected to the ground of the system.
Input Input Input Ground
Power Supply Power Supply Inputs to the Device. Hardware Store Busy (HSB\). When LOW this output indicates that a hardware store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor Input/Output keeps this pin HIGH if not connected (connection optional). After each store operation HSB\ is driven HIGH for short time with standard output high current. AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to Power Supply nonvolatile elements. (leave pin open if caps mounted on package) No Connect No Connect. This pin is not connected to the die.
HSB\
VCAP NC
AS8nvC512K32 Rev. 0.0 08/09
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Device Operation
The AS8nvC512K32 nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The AS8nvC512K32 supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the Truth Table For SRAM Operations for a complete description of read and write modes.
AS8nvC512K32
nvSRAM
for automatic store operation. Refer to DC Electrical Characteristics for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull up should be placed on WE\ to hold it inactive during power up. This pull up is effective only if the WE\ signal is tri-state during power up. Many MPUs tri-state their controls on power up. This should be verified when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE\ held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and hardware store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB\ signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 2. AutoStore Mode
Vcc
SRAM Read
The AS8nvC512K32 performs a read cycle when CE\ and OE\ are LOW and WE\ and HSB\ are HIGH. The address specified on pins A0-18 determines which of the 524,288 data bytes. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE\ or OE\, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE\ or OE\ is brought HIGH, or WE\ or HSB\ is brought LOW.
0.1uF
10kOhm
Vcc
WE1-4
VCAP
SRAM Write
A write cycle is performed when CE\ and WE\ are LOW and HSB\ is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE\ or WE\ goes HIGH at the end of the cycle. The data on the common I/O pins DQ0-31 are written into the memory if the data is valid tSD before the end of a WE\ controlled write or before the end of an CE\ controlled write. It is recommended that OE\ be kept HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE\ is left LOW, internal circuitry turns off the output buffers tHZWE after WE\ goes LOW.
VSS
VCAP
Hardware STORE Operation
The AS8nvC512K32 provides the HSB\ 6 pin to control and acknowledge the STORE operations. Use the HSB\ pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the AS8nvC512K32 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB\ pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated. After HSB\ goes LOW, the AS8nvC512K32 continues SRAM operations for tDELAY. If a write is in progress when HSB\ is pulled LOW it is enabled a time, tDELAY to complete. However, any SRAM write cycles requested after HSB\ goes LOW are inhibited until HSB\ returns HIGH. In case the write latch is not set, HSB\ is not driven LOW by the AS8nvC512K32. But any SRAM read and write cycles are inhibited until HSB\ is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the AS8nvC512K32 continues to drive the HSB\ pin LOW, releasing it only when the STORE is complete. When the STORE operation is completed, the AS8nvC512K32 remains disabled until the HSB\ pin returns HIGH. Leave the HSB\ unconnected if it is not used..
AutoStore Operation
The AS8nvC512K32 stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB\; Software Store activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the AS8nvC512K32. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2 shows the proper connection of the storage capacitor (VCAP)
AS8nvC512K32 Rev. 0.0 08/09
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Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver.
AS8nvC512K32
nvSRAM
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The AS8nvC512K32 software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following read sequence must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
Mode Selection
CE\1 4 H L L L WE\1 4 X H L H OE\ 13 X L X L A15 A0 7 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable I/O0 31 Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Power Standby Active Active Active 8
Notes 7. While there are 19 address lines on the AS8nvC512K32, only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are don't care. 8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 13.WE\ must be HIGH during SRAM read cycles.
AS8nvC512K32 Rev. 0.0 08/09
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Mode Selection (continued)
CE\1 4 L WE\1 4 H OE\ L
13
AS8nvC512K32
I/O0 31 Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
nvSRAM
A15 A0
7
Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall
Power Active 8
L
H
L
0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63
Active ICC2 8
L
H
L
Active 8
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The AS8nvC512K32 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the AS8nvC512K32 is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.
AS8nvC512K32 Rev. 0.0 08/09
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Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: The nonvolatile cells in this nvSRAM product are delivered from Austin Semiconductor with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
AS8nvC512K32
nvSRAM
Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Austin Semiconductor to understand any impact on the VCAP voltage level at the end of a tRECALL period.
AS8nvC512K32 Rev. 0.0 08/09
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .............................................-65C to +150C Maximum Accumulated Storage Time At 150C Ambient Temperature...............................1000h At 85C Ambient Temperature.............................20 Years Ambient Temperature with Power Applied ......................................................-55C to +125C Supply Voltage on Vcc Relative to GND................... -0.5V to 6.0V Voltage Applied to Outputs in High-Z State ............................................... -0.5V to Vcc + 0.5V Input Voltage .................................................. -0.5V to Vcc + 0.5V Transient Voltage (<20 ns) on
AS8nvC512K32
nvSRAM
Any Pin to Ground Potential............................-2.0V to Vcc + 2.0V Package Power Dissipation Capability (TA = 25C) ...........................................................1.0W Surface Mount Pb Soldering Temperature (3 Seconds)......................................................+260C DC Output Current (1 output at a time, 1s duration) ..............15 mA Static Discharge Voltage .................................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current............................................................. > 200 mA
Operating Range
Range Military Industrial Ambient Temperature Vcc o o 55 C to +125 C 5.0V 10% o o 40 C to +85 C 5.0V 10%
DC Electrical Characteristics
Over the Operating Range (VCC = 5.0V 10%)
Parameter Description Test Conditions tRC = 20 ns tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) Min Max 450 400 350 350 325 275 60 Unit mA mA mA mA mA mA mA
Military
ICC1
Average VCC Current
Industrial Average VCC Current during STORE Average Vcc Current at tRC= 200 ns, 5V, 25C typical Average VCAP Current during AutoStore Cycle VCC Standby Current Input Leakage Current (except HSB\) Input Leakage Current (for HSB\) Off State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage
11
ICC2
All Inputs Don't Care, VCC = Max Average current for duration tSTORE All I/P cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). All Inputs Don't Care, VCC = Max Average current for duration tSTORE CE \ (VCC - 0.2V). All others VIN 0.2V or (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. VCC = Max, VSS VIN VCC VCC = Max, VSS VIN VCC VCC = Max, VSS VOUT VCC, CE\ or OE\ VIH or BHE\/BLE\ VIH or WE\ VIL 5
ICC3 9
220 mA
ICC4
40
mA
ISB
40
mA
5
A A A V V V
IIX 10
400 10 10 2.2 VSS 0.3 10 VCC + 0.3 0.8
IOZ VIH VIL VOH VOL VCAP
IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 10.0V Rated
2.4 0.45 80 180
V F
Storage Capacitor
Notes 9. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25C (room temperature), and VCC = 5V. Not 100% tested. 10. The HSB\ pin has IOUT = -8 uA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. 11. VCAP (storage capacitor) nominal value is 88 uF total cap.
AS8nvC512K32 Rev. 0.0 08/09
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Data Retention and Endurance
Parameter DATAR NVC Description Data Retention Nonvolatile STORE Operation Min 20 200 Unit Years Cycles
AS8nvC512K32
nvSRAM
Capacitance
In the following table, the capacitance parameters are listed. 12
Parameter Description CIN Input Capacitance (Addr, OE\, HSB\) CIN COUT(DQ) Input Capacitance (CE\1 4, WE\1 4 I/O Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V
Min 50 20 25
Unit pF pF pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed. 12
Parameter
JA
JC
Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case)
Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.
44 TSOP II TBD TBD
44 Gullwing Unit TBD TBD
o
C/W C/W
o
AC Test Loads
577 5.0V OUTPUT 30 pF R2 789 R1 577 5.0V OUTPUT 5 pF R2 789 R1
for tri-state specs
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times (10% - 90%)........................ <3 ns Input and Output Timing Reference Levels .................... 1.5V
Note 12. These parameters are guaranteed but not tested.
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AC Switching Characteristics
Parameters Austin Semi Alt Parameters Parameters Description SRAM Read Cycle tACE tACS Chip Enable Access Time tRC
13
AS8nvC512K32
45 ns Min Max 45 45 25 12 45 20 2 2 10 15 0 10 15 0 25 12 45 20 0 10 15 45 30 30 15 0 30 0 0 10 15 2 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
nvSRAM
20 ns Min Max 20 20 20 10 2 2 8 0 8 0 20 10 0 8 20 15 15 8 0 15 0 0 8 2 15 2 20 25 20 20 10 0 20 0 0 0 0 0 2 2 25 Min
25 ns Max 25
tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS
Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Active Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to End of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write
tAA 14 tDOE tOHA 14 tLZCE 12, 15 tHZCE 12, 15 tLZOE 12, 15 tHZOE 12, 15 tPU 12 tPD
12
tDBE tLZBE 12 tHZBE 12 SRAM Write Cycle tWC tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE tBW
12, 15, 16
tWP tCW tDW tDH tAW tAS tWR tWZ tOW
tLZWE 12, 15
Switching Waveforms
SRAM Read Cycle #1: Address Controlled 13, 14, 17
tRC Address Address Valid tAA Data Output Previous Data Valid tOHA
Notes 13.WE\ must be HIGH during SRAM read cycles. 14. Device is continuously selected with CE\, OE\ LOW. 15.Measured 200 mV from steady state output voltage. 16. If WE\ is LOW when CE\ goes LOW, the outputs remain in the high impedance state. 17. HSB\ must remain HIGH during read and write cycles.
Output Data Valid
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AS8nvC512K32
nvSRAM
SRAM Read Cycle #2: CE\ and OE\ Controlled 3, 13, 17
Address Address Valid tRC tACE CE tAA tLZCE OE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance tPU ICC Standby Active Output Data Valid tPD tDOE tHZBE tHZOE tHZCE
SRAM Write Cycle #1: WE\ Controlled 3, 16, 17,18
tWC Address Address Valid tSCE CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input tHZWE Data Output Previous Data tHD Input Data Valid tLZWE High Impedance tHA
Note 18. CE\ or WE\ must be >VIH during address transitions.
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SRAM Write Cycle #2: CE\ Controlled3, 16, 17, 18
tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA
AS8nvC512K32
nvSRAM
AS8nvC512K32 Rev. 0.0 08/09
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AutoStore/Power Up RECALL
Parameters Description 19 tHRECALL Power Up RECALL Duration tSTORE 20 tDELAY
21
AS8nvC512K32
45 ns Min Max 20 10 25 3.65 150 1.9 5 500 1.9 5 500
nvSRAM
20 ns Min Max 20 10 20 3.65 150 1.9 5 500
25 ns Min Max 20 10 25 3.65 150
Unit ms ms ns V s V s ns
STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level VCC Rise Time HSB\ Output Driver Disable Voltage HSB\ To Output Active Time HSB\ High Active Time
VSWITCH tVCCRISE VHDIS tLZHSB tHHHD
12
Switching Waveforms
AutoStore or Power Up RECALL22
VSWITCH VHDIS
V VCCRISE tHHHD HSB OUT
Note20
tSTORE tHHHD
Note20
tSTORE Note23
tDELAY tLZHSB tDELAY POWERUP RECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT Autostore POWER-UP RECALL Read & Write POWER DOWN Autostore tLZHSB
Autostore
tHRECALL
tHRECALL
Notes 19. tHRECALL starts from the time VCC rises above VSWITCH. 20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place. 21. On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY. 22. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 23. HSB\ pin is driven HIGH to VCC only by internal 100 kOhm resistor, HSB\ driver is disabled.
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Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.24, 25
AS8nvC512K32
nvSRAM
Parameters Description tRC STORE/RECALL Initiation Cycle Time tSA tCW tHA tRECALL Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration
20 ns Min Max 20 0 15 0 200
25 ns Min Max 25 0 25 0 200
45 ns Min Max 45 0 30 0 200
Unit ns ns ns ns s
Switching Waveforms
CE\ and OE \Controlled Software STORE/RECALL Cycle25
g AutoStore
Enable/Disable yCycle
Notes 24. The software sequence is clocked with CE\ controlled or OE\ controlled reads. 25. The six consecutive addresses must be read in the order listed in the MODE Selection Table. WE\ must be HIGH during all six consecutive cycles.
AS8nvC512K32 Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
AUSTIN SEMICONDUCTOR, INC. ADVANCE INFORMATION Austin Semiconductor, Inc.
Truth Table For SRAM Operations
HSB\ should remain HIGH for SRAM Operations.
AS8nvC512K32
nvSRAM
For x32 Configuration CE\1 4 WE\1 4 OE\ H X X L H L L H H L L X
Inputs / Outputs High Z Data Out (DQ0 DQ31) High Z Data In (DQ0 DQ31)
Mode Deselect / Power Down Read Output Disabled Write
Power Standby Active Active Active
AS8nvC512K32 Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
AUSTIN SEMICONDUCTOR, INC. ADVANCE INFORMATION Austin Semiconductor, Inc.
AS8nvC512K32
nvSRAM
Ceramic 68 Quad Flatpak
AS8nvC512K32 Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
AUSTIN SEMICONDUCTOR, INC. ADVANCE INFORMATION Austin Semiconductor, Inc.
Ordering Information
ASI Part Number AS8nvC512K32QC 20XT AS8nvC512K32QC 25XT AS8nvC512K32QC 45XT AS8nvC512K32Q 20XT AS8nvC512K32Q 25XT AS8nvC512K32Q 45XT Configuration 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32
AS8nvC512K32
nvSRAM
Package Type Speed Operating Range 68 Quad Flatpak 20 XT 68 Quad Flatpak 25 XT 68 Quad Flatpak 45 XT 68 Quad Flatpak 20 IT 68 Quad Flatpak 25 IT 68 Quad Flatpak 45 IT
QC = Capacitors& resistors mounted on package Q= No capacitor or resistor
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Military Temperature Range
Temperature -40oC to +85oC -55oC to +125oC
AS8nvC512K32 Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
AUSTIN SEMICONDUCTOR, INC. ADVANCE INFORMATION Austin Semiconductor, Inc.
DOCUMENT TITLE 512K x 32 nvSRAM 5.0V High Speed SRAM with Non-Volatile Storage REVISION HISTORY Rev # 0.0 History Document Creation Release Date August 2009
AS8nvC512K32
nvSRAM
Status Advance
AS8nvC512K32 Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17

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